View EM78871H_1237088.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

EM78871
8-BIT MICRO-CONTROLLER
Version 1.5
ELAN MICROELECTRONICS CORP. No. 12, Innovation 1st RD., Science-Based Industrial Park Hsin Chu City, Taiwan, R.O.C. TEL: (03) 5639977 FAX: (03) 5630118
EM78871 8-bit Micro-controller
Version History
Specification Revision History Content Preliminary Version EM78871 1.0 Initial version 1.1 Remove Package 1.2 Modify Idle mode current 1.3 Modify Code option 1.4 Modify Package type 1.5 Remove Idle Mode Function Release Date
2003/06/05 2003/06/18 2003/08/07 2004/02/09 2004/03/15 2004/08/23
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 2
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
User Application Note
1. ROM, OTP, ICE ROM EM78871 OTP EM78P808 ICE ICE 808 EM78P808 VDD or 2V O O EM78871 VDD or 2V X X (R6 page1 bit0-7&R7 page1 bit0- 7&R8 page1 bit0-7& R9 page1 bit0-1 unused) X(unused) X(unused) X(unused)
2. The difference between ICE 808 , EM78P808 and EM78871 are listed in the table
ICE 808 Comparator reference voltage VDD Stack pointer O Data Rom O
RE page1 bit4 IOCE page1 bit0-1 RE page1 bit7-6 IOCE page2 bit0-2, bit4-6 code option bit0
O O O
O O O
3. "While switching main clock (regardless of high freq to low freq or on the other hand), adding 6 instructions delay (NOP) is required." 4. For DATA RAM least address(A0~A7), when using "INC" instruction and overflow occur, the middle address will auto_increase. If using "DEC" instruction and least address from 0x00 0xFF, the middle address can't auto_decrease. 5. When Tip and Ring signals come, user cans choice one of FSK or DTMF receiver to decode. The Operation Registers Setup as follows: FSK DTMF FSK or DTMF (RA PAGE0 bit 3) (IOC9 PAGE1 bit 7) 0 0 All decoder off 0 1 DTMF on FSK off 1 X FSK on (don't care) DTMF off 6.Die Pin difference Pin EGIN1 EGIN2 Power PAD Gnd PAD EM78P808 136 pins V V 2(VDD pin & AVDD pin) 2(AVSS pin & GND pin) EM78871 132 pins X X 1(VDD/AVDD pin) 1(AVSS/GND pin)
7.Don't switch to sleep mode from normal mode directly. Before do this, please switch to green mode first. 8.Don't allow enable Idle Mode Function. (RA Page0 bit 7 don't allow set to 1)
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 3
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
I.General Description
The EM78871 is an 8-bit CID (Call Identification) RISC type microprocessor with low power, high speed CMOS technology. Integrated onto a single chip are on chip watchdog (WDT), RAM, program ROM, programmable real time clock/counter, external/internal interrupt, power down mode, LCD driver, FSK decoder, Call waiting decoder, DTMF receiver, Programming Tone generator, build-in KEY TONE clock generation, Comparator and tri-state I/O. The EM78871 provides a single chip solution to design a CID of calling message display.
II.Feature
CPU Operating voltage range : 2.2V~5.5V(Normal mode), 2.0V~5.5V(Green mode) 32KN 13 on chip Program ROM 4KN 8 on chip data RAM 144 byte working register Up to 51 bi-directional tri-state I/O ports (32 shared with LCD Segment pins) IO with internal Pull high, wake-up and interrupt functions STACK: 32 level stack for subroutine nesting TCC: 8-bit real time clock/counter (TCC) with 8-bit prescaler COUNTER1: 8-bit counter with 8-bit prescaler can be an interrupt source COUNTER2: 8-bit counter with 8-bit prescaler can be an interrupt source Watch Dog : Programmable free running on chip watchdog timer CPU modes: Mode CPU status Main clock 32.768kHz clock status Sleep mode Turn off Turn off Turn off Green mode Turn on Turn off Turn on Normal mode Turn on Turn on Turn on E 13 interrupt source , 8 external , 5 internal E Key Scan : Port key scan function up to 16x4 keys E Sub-Clock: 32.768KHz crystal E Main-clock: 3.5862MHz multiplied by 0.25, 0.5, 1 or 3 generated by internal PLL E Key tone output :4KHz, 2KHz ,1KHz (shared with IO) E Comparator: 3-channel comparators: internal (16 level) or external reference voltage. (shared with IO) E Serial Peripheral Interface (SPI): Interrupt flag available for the read buffer full, Programmable baud rates of communication, Three-wire synchronous communication. (shared with IO) Current D/A E Operation Voltage : 2.5Va 5.5V E 7-bit resolution and 3-bit output level control E Current DA output can drive speaker through a transistor for sound playing. (shared with IO) Programmable Tone Generators E Operation Voltage 2.2Va 5.5V E Programmable Tone1 and Tone2 generators E Independent single tone generation for Tone1 and Tone2 E Mixed dual tone generation by Tone1 and Tone2 with 2dB difference E Can be programmed for DTMF tone generation E Can be programmed for FSK signal (Bell202 or V.23) generation CID E Operation Voltage 2.7Va 5.5V for FSK E Operation Voltage 2.7Va 5.5V for DTMF receiver E Compatible with Bellcore GR-30-CORE (formerly as TR-NWT-000030) E Compatible with British Telecom (BT) SIN227 & SIN242 E FSK demodulator for Bell 202 and ITU-T V.23 (formerly as CCITT V.23) CALL WAITING E Operation Voltage 2.6Va 5.5V E E E E E E E E E E E E
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 4
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
Compatible with Bellcore special report SR-TSV-002476 Call-Waiting (2130Hz plus 2750Hz) Alert Signal Detector Good talkdown and talkoff performance Sensitivity compensated by adjusting input OP gain LCD (8x80, 9x80, 16x80, 24x72) E Maximum common driver pins : 16/24 E Maximum segment driver pins : 80(SEG0..SEG79)/72(SEG8..SEG79) E Shared COM16 ~ COM23 pins with SEG0 ~ SEG7 pins E 1/4 bias for 8, 9 and 16 common mode and 1/5 bias for 24 common mode E 1/8, 1/9, 1/16, 1/24 duty E 16 Level LCD contrast control (software) E Internal resistor circuit for LCD bias E Internal voltage follower for better display Die type E 132 pin die : EM78871H E 128 pin package : (EM78871AQ POVD disable, EM78871BQ POVD enable) E E E E
III.Application
1. adjunct units 2. answering machines 3. feature phones
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 5
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
IV.Pin Configuration
SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG10 SEG9 SEG8 COM23/SEG7 COM22/SEG6 COM21/SEG5 COM20/SEG4 COM19/SEG3 COM18/SEG2 COM17/SEG1 COM16/SEG0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 XIN XOUT AVDD/ VDD PLLC TONE TIP RING CWGS CWIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 132 131 130 129 128 127 126 125 124 123 122 121 120 SEG25 SEG26 SEG27
119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48/PB0 SEG49/PB1 SEG50/PB2 SEG51/PB3 SEG52/PB4 SEG53/PB5 SEG54/PB6 SEG55/PB7 SEG56/PC0 SEG57/PC1 SEG58/PC2 SEG59/PC3 SEG60/PC4 SEG61/PC5 SEG62/PC6 SEG63/PC7 SEG64/P80 SEG65/P81 SEG66/P82 SEG67/P83 SEG68/P84 SEG69/P85 SEG70/P86 SEG71/P87 SEG72/P90 SEG73/P91 SEG74/P92 SEG75/P93 SEG76/P94 SEG77/P95 SEG78/P96
39 40 41 42 43 44 45 46 47 48 49 50 51
37 38
AVSS/ GND P57
P56/EST P55/STGT P60/SCK P61/SDO P62/SDI P63/CMP1 P64/CMP2 P65/CMP3 P66/DAOUT
Fig.1.1
Pin assignment (132-Pin die)
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 6
P67/KTONE TEST /RESET
EM78871H
P77/INT2 P76/INT1 P75/INT1 P74/INT1 P73/INT0 P72/INT0 P71/INT0 P70/INT0 VC1 VC2 VC3 VC4 VC5 SEG79/P97
52 53 54
55 56 57 58 59 60 61 62 63 64
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG12 SEG11 SEG10 SEG9 SEG8 COM23/SEG7 COM22/SEG6 COM21/SEG5 COM20/SEG4 COM19/SEG3 COM18/SEG2 COM17/SEG1 COM16/SEG0 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 XIN XOUT VDD/AVDD PLLC TONE TIP RING CWGS CWIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 128 127 126 125 124 123 122 121 120 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
39 40 41 42 43 44 45 46 47 48 49 50 51
52 53 54
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 7
GND/AVSS P57 P56/EST P55/STGT P60/SCK P61/SDO P62/SDI P63/CMP1 P64/CMP2 P65/CMP3 P66/DAOUT P67/KTONE TEST /RESET P77/INT2 P76/INT1
EM78871AQ/BQ
Fig.1.2
Pin assignment (128-Pin QFPA)
P75/INT1 P74/INT1 P73/INT0 P72/INT0 P71/INT0 P70/INT0 VC1 VC2 VC3 VC4
55 56 57 58 59 60 61 62 63 64
SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48/PB0 SEG49/PB1 SEG50/PB2 SEG51/PB3 SEG52/PB4 SEG53/PB5 SEG54/PB6 SEG55/PB7 SEG60/PC4 SEG61/PC5 SEG62/PC6 SEG63/PC7 SEG64/P80 SEG65/P81 SEG66/P82 SEG67/P83 SEG68/P84 SEG69/P85 SEG70/P86 SEG71/P87 SEG72/P90 SEG73/P91 SEG74/P92 SEG75/P93 SEG76/P94 SEG77/P95 SEG78/P96 SEG79/P97 VC5
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
V.Functional Block Diagram
CP CPU U
DATA RAM DATA RAM CONTROL CONTROL REGISTER REGISTER
TIMING TIMING CONTROL CONTROL
LCD DRIVER LCD DRIVER
LCD
TIMER TCC COUNTER 1 COUNTER 2 WDT
IO IO PORT PORT
I/O
DATA ROM PROGRAM PROGRAM ROM ROM
FSK DECODER CURRENT DA Call waiting decoder DTMF receiver DUAL TONE GENERATOR KEY TONE COMPARATOR SERIAL I/O
Fig.2 Block diagram1
Xin Xout PLLC WDT timer Oscillator timing control R1(TCC) Control sleep and wake-up on I/O port GENERAL RAM R4 prescalar Interruption control Instruction register R3 R5 ALU ROM R2 STACK
ACC
Instruction decoder
DATA & CONTROL BUS
DATA RAM PORT5 FSK DECODER FSK DECODER Call waiting decoder DTMF receiver DTMF receiver DUAL TONE GENERATOR DUAL TONE GENERATOR KEY TONE KEY TONE SERIAL I/O SERIAL I/O COMPARATOR COMPARATOR CURRENT DA CURRENT DA OP IOC5 R5 PORT6 IOC6 R6 PORT7 IOC7 R7 PORT8 IOC8 R8 PORT9 IOC9 R9 PORTB IOCB RB PORTC IOCC RC
P55~P57
P60~P67
P70~P77
P80~P87
P90~P97
PB0~PB7
PC0~PC7
Fig.3 Block diagram2
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 8
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
VI.Pin Descriptions
PIN POWER VDD AVDD GND AVSS CLOCK XIN XOUT PLLC LCD COM0..COM15 SEG0..SEG7 SEG8...SEG47 SEG48..SEG55 SEG56..SEG63 SEG64..SEG71 SEG72..SEG79 VC1..VC5 I/O POWER DESCRIPTION Digital power Analog power They connect together when package as 128 pin QFP. Digital ground Analog ground They connect together when package as 128 pin QFP. Input pin for 32.768 kHz oscillator Output pin for 32.768 kHz oscillator Phase loop lock capacitor, connect a capacitor 0.01u to 0.047u with GND Common driver pins of LCD drivers Segment driver pins of LCD drivers SEG0 to SEG7 are shared with COM16 to COM23 SEG48 to SEG79 are shared with IO PORT.
POWER
I O I
O O(COM16..COM23) O O (I/O : PORTB) O (I/O : PORTC) O (I/O : PORT8) O (I/O : PORT9) I
Reference voltage input. Each one connect a capacitor (0.1u) with GND.
FSK , TONE , KTONE TIP I RING I TONE KTONE CW CWGS CWIN DTMF receiver EST O O (PORT67) O I
Should be connected with TIP side of twisted pair lines for FSK. Should be connected with RING side of twisted pair lines for FSK. Dual tone output pin Key tone output. Shared with PORT67. Gain adjustment of single-ended input OP Amp Single-ended input OP Amp for call waiting decoder
O
STGT
I/O
Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause EST to return to a logic low. This pin shared with PORT56. Steering input/guard time output (bi-directional). A voltage greater than Vtst detected at ST causes the device to register the detected tone-pair and update the output latch. A voltage less than Vtst frees the device to accept a new tone-pair. The GT output acts to reset the external steering time-constant; its state is a function of EST and the voltage on ST . This pin shared with PORT55. Master: output pin, Slave: input pin. This pin shared with PORT60. Output pin for serial data transferring. This pin shared with PORT61. Input pin for receiving data. This pin shared with PORT62.
SERIAL IO SCK SDO SDI Comparator
IO (PORT60) O (PORT61) I (PORT62)
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 9
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
CMP1 CMP2 CMP3 CURRENT DA DAOUT I I I (PORT63) (PORT64) (PORT65) Comparator input pins. Shared with PORT63, PORT64 and PORT65.
O (PORT66)
Current DA output pin. It can be a control signal for sound generating. Shared with PORT66. PORT 5 can be INPUT or OUTPUT port each bit. PORT 6 can be INPUT or OUTPUT port each bit. Internal pull high. PORT 7 can be INPUT or OUTPUT port each bit. Internal Pull high function. Auto key scan function. Interrupt function. PORT 8 can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. PORT 9 can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. PORT B can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. PORT C can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. Interrupt sources which has the same interrupt flag. Any pin from PORT70 to PORT73 has a falling edge signal, it will generate a interruption. Interrupt sources which has the same interrupt flag. Any pin from PORT74 to PORT76 has a falling edge signal, it will generate a interruption. Interrupt source. Once PORT77 has a falling edge or rising edge signal (controlled by CONT register), it will generate a interruption. Test pin into test mode for factory test only. Connect it ground in application. Low reset
IO P55 ~P57 P60 ~P67 P70 ~ P77
I/O I/O I/O
P80 ~ P87 P90 ~ P97 PB0 ~ PB7 PC0 ~ PC7 INT0
I/O I/O I/O I/O PORT70..73
INT1
PORT74..76
INT2
PORT77
TEST /RESET
I I
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 10
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
VII.Functional Descriptions VII.1 Operational Registers
ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 : 1F 20 : 3F R0 R1(TCC buffer) R2(PC) R3(7) R3(STATUS) R4(RSR, BANK SELECT R5(PORT57..PORT55 Program ROM PAGE) R6(PORT6) R7(PORT7) R8(PORT8) R9(PORT9) RA(CPU MODE,CLOCK, FSK,WDT control) RB(PORTB) RC(PORTC) RD(Comparator control) RE(Key scan , LCD control) RF(Interrupt flag) 16 byte COMMON REGISTER LCD RAM BANK0 , BANK1, BANK2 ,BANK3 32X8 32X8 32X8 32X8 COMMOM REGISTER RA PAGE1 => address RB PAGE1 =>data
R4(7,6)
REGISTER (PAGE0)
REGISTER (PAGE1)
CONTROL REGISTER (PAGE0)
CONTROL REGISTER (PAGE1)
R3(5,6)
R4(SPI status and control R5(SPI data buffer) R6 (Unused) R7(Unused) R8(Unused) R9(EDD,LCDA8) RA(LCD RAM address) RB (LCD RAM data buffer) RC(DATA RAM data buffer) RD(DATA RAM address address 7 .. address 0) RE(,DATA RAM address address 11 .. address 8) IOC5(IOC55,56,57,P8S, P9S,PBS,PCS) IOC6(PORT6 IO control) IOC7 (PORT7 IO control) IOC8 (PORT8 IO control) IOC9 (PORT9 IO control IOCA(COUNTER1,2, prescaler and source) IOCB(PORTB IO control) IOCC(PORTC IO control) IOCD(COUNTER1 PRESET) IOCE(COUNTER2 PRESET) IOCF(Interrupt control) IOC5(Key tone, LCD bias control) IOC6 (current DA) IOC7(key strobe , seg7 .. seg0) IOC8(key strobe, seg15.. seg8) IOC9(DTMF receiver control) IOCA(PORT7 pull high) IOCB(PORT6 pull high) IOCC(Tone1) IOCD(Tone2) IOCE
CONTROL REGISTER (PAGE2) R3(5,6)
DATA RAM RD PAGE1 => address7..0 RE PAGE1 => address11..8 RC PAGE1 =>data
IOC5 ( Stack Pointer ) IOC6 (Port s/w, LCDDV, CDAL) IOCE
Fig.4 control register configuration
VII.2 Operational Register Detail Description
R0 (Indirect Addressing Register)
R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4). Example: Mov a,@0x20 ;store a address at R4 for indirect addressing Mov 0x04,A Mov a,@0xAA ;write data 0xAA to R20 at bank0 through R0 Mov 0x00,A
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 11
8/23/04 (V1.5)
EM78871 8-bit Micro-controller R1 (TCC)
TCC data buffer. Increased by 16.38KHz or by the instruction cycle clock (controlled by CONT register). Written and read by the program as any other register.
R2 (Program Counter)
The structure is depicted in Fig. 5. Generates 32K x 13 on-chip PROGRAM ROM addresses to the relative programming instruction codes. "JMP" instruction allows the direct loading of the low 10 program counter bits. "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack. "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. "MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to "0''. "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are cleared to "0''. "TBL" allows a relative address be added to the current PC, and contents of the ninth and tenth bits don't change. The most significant bit (A10~A14) will be loaded with the content of bit PS0~PS3 in the status register (R5) upon the execution of a "JMP'', "CALL'', "ADD R2,A'', or "MOV R2,A'' instruction. If a interrupt trigger, PROGRAM ROM will jump to address8 at page0. The CPU will store ACC,R3 status and R5 PAGE automatically, it will restore after instruction RETI.
R5(PAGE)
CALL and INTERRUPT A9 A8 A7~A0 RET RETL RETI STACK1 STACK2 STACK3 STACK4 STACK5 STACK6 STACK7 STACK8 STACK9 : : STACK30 STACK31 STACK32
PC
A14 A13 A12 A11 A10
00000 PAGE0 0000~03FF 00001 PAGE1 0400~07FF 00010 PAGE2 0800~0BFF
store ACC,R3,R5(PAGE) restore
11110 11111
PAGE30 7800~7BFF PAGE31 7C00~7FFF
Fig.5 Program counter organization
R3 (Status Register)
7 6 5 4 3 2 1 0 PAGE IOCP1S IOCPAGE T P Z DC C Bit 0 (C) : Carry flag Bit 1 (DC) : Auxiliary carry flag Bit 2 (Z) : Zero flag Bit 3 (P) : Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Bit 4 (T) : Time-out bit. Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT timeout.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 12
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
EVENT WDT wake up from sleep mode WDT time out (not sleep mode) /RESET wake up from sleep Power up Low pulse on /RESET T 0 0 1 1 x P 0 1 0 1 X x : don't care REMARK
Bit 5(IOCPAGE) : change IOC5 ~ IOCE to another page Please refer to Fig.4 control register configuration for details. 0/1 page0 / page1 Bit 6(IOCP1S) : change IOC PAGE1 and PAGE2 to another option register Please refer to Fig.4 control register configuration for details. 0/1 page1 /page2 Bit 6(IOCP1S) Bit 5 (IOCPAGE) X 0 0 1 1 1 Bit 7(PAGE) : change R4 ~ RE to another page Please refer to Fig.4 control register configuration for details. 0/1 page0 / page1 PAGE SELECT PAGE 0 PAGE 1 PAGE 2
R4 (RAM selection for common registers R20 ~ R3F, SPI) PAGE0 (RAM selection register)
7 6 5 4 3 2 1 0 RB1 RB0 RSR5 RSR4 RSR3 RSR2 RSR1 RSR0 Bit 0 ~ Bit 5 (RSR0 ~ RSR5) : Indirect addressing for common registers R20 ~ R3F RSR bits are used to select up to 32 registers (R20 to R3F) in the indirect addressing mode. Bit 6 ~ Bit 7 (RB0 ~ RB1) : Bank selection bits for common registers R20 ~ R3F These selection bits are used to determine which bank is activated among the 4 banks for 32 register (R20 to R3F).. Please refer to Fig.4 control register configuration for details.
PAGE1 (SPI control register)
7 RBF 6 SPIE 5 SRO 4 SE 3 SCES 2 SBR2 1 SBR1 0 SBR0
Fig. 6 shows how SPI to communicate with other device by SPI module. If SPI is a master controller, it sends clock through the SCK pin. An 8-bit data is transmitted and received at the same time. If SPI, however, is defined as a slave, its SCK pin could be programmed as an input pin. Data will continue to be shifted on a basis of both the clock rate and the selected edge.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 13
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
SDO SDI
Master Device
R5 page1
SPIR register SPIW register
Salve Device
SPIS Reg
Bit7 Bit 0
SDI
SDO
SPI module
SCK
SCK
Fig.6 Single SPI Master / Salve Communication
Bit 0 ~ Bit 2 (SBR0 ~ SBR2) : SPI baud rate selection bits SBR2 0 0 0 0 1 1 1 1 SBR1 0 0 1 1 0 0 1 1 SBR0 0 1 0 1 0 1 0 1 Mode Master Master Master Master Master Master Slave X Baud rate Fsco Fsco/2 Fsco/4 Fsco/8 Fsco/16 Fsco/32
Fsco = CPU instruction clock For example : If PLL enable and RA PAGE0 (Bit5,Bit4)=(1,1), instruction clock is 3.58MHz/2 Fsco=3.5862MHz/2 If PLL enable and RA PAGE0 (Bit5,Bit4)=(0,0), instruction clock is 0.895MHz/2 Fsco=0.895MHz/2 If PLL disable, instruction clock is 32.768kHz/2 Fsco=32.768kHz/2. Bit 3 (SCES) : SPI clock edge selection bit 1 Data shifts out on falling edge, and shifts in on rising edge. Data is hold during the high level. 0 Data shifts out on rising edge, and shifts in on falling edge. Data is hold during the low level. Bit 4 (SE) : SPI shift enable bit 1 Start to shift, and keep on 1 while the current byte is still being transmitted. 0 Reset as soon as the shifting is complete, and the next byte is ready to shift. This bit has to be reset in software. Bit 5 (SRO) : SPI read overflow bit 1 A new data is received while the previous data is still being hold in the SPIB register. In this situation, the data in SPIS register will be destroyed. To avoid setting this bit, users had better to read SPIB register even if the transmission is implemented only. 0 No overflow This can only occur in slave mode. Bit 6 (SPIE) : SPI enable bit 1 Enable SPI mode 0 Disable SPI mode Bit 7 (RBF) : SPI read buffer full flag 1 Receive is finished, SPIB is full. 0 Receive is not finish yet, SPIB is empty.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 14
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
Read R5 RBF RBFI SPIWC
Write R5
SPIR reg.
SPIW reg.
set to 1 SPIE Buffer Full Detector
SDI
SDI/P62
MUX
SPIS reg.
PORT62 bit 0 SDO
shift right
bit 7
SDO/P61
SPIC reg. (R4 page1)
MUX
PORT61
Edge Select SPIE 0
3
SBR0 ~SBR2
SBR2~SBR0
3 2
Noise Filter Clock Select
Tsco
16.38kHz
Prescaler 4, 8, 16, 32, 64, 128
Edge Select
SCK PORT60
M UX
SCK/P60
SCK
SPIE
Fig.7 SPI structure SPIC reg. : SPI control register SDO/P61 : Serial data out SDI/P62 : Serial data in SCK/P60 : Serial clock RBF : Set by buffer full detector, and reset in software. RBFI : Interrupt flag. Set by buffer full detector, and reset in software. Buffer Full Detector : Sets to 1, while an 8-bit shifting is complete. SE : Loads the data in SPIW register, and begin to shift SPIE : SPI control register SPIS reg. : Shifting byte out and in. The MSB will be shifted first. Both the SPIS register and the SPIW register are loaded at the same time. Once data being written to, SPIS starts transmission / reception. The received data will be moved to the SPIR register, as the shifting of the 8-bit data is complete. The RBF (Read Buffer Full ) flag and the RBFI(Read Buffer Full Interrupt) flag are set. SPIR reg. : Read buffer. The buffer will be updated as the 8-bit shifting is complete. The data must be read before the next reception is finished. The RBF flag is cleared as the SPIR register read. SPIW reg. : Write buffer. The buffer will deny any write until the 8-bit shifting is complete. The SE bit will be kept in 1 if the communication is still under going. This flag must be cleared as the shifting is finished. Users can determine if the next write attempt is available. SBR2 ~ SBR0: Programming the clock frequency/rates and sources. Clock select : Selecting either the internal instruction clock or the external 16.338KHz clock as the shifting clock. Edge Select : Selecting the appropriate clock edges by programming the SCES bit
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 15
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
SCK
(SCES=0)
SCK
(SCES=1) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SDO
SDI
RBF
Shift data in
Shift data out
Clear by software
Fig.8 SPI timing
R5 (PORT5 I/O data, Program page selection, SPI data) PAGE0 (PORT5 I/O data register, Program page register)
7 6 5 4 3 R57 R56 R55 PS4 PS3 Bit 0 ~ Bit 4 (PS0 ~ PS4) : Program page selection bits 2 PS2 1 PS1 0 PS0
PS4 PS3 PS2 PS1 PS0 Program memory page (Address) 0 0 0 0 0 Page 0 0 0 0 0 1 Page 1 0 0 0 1 0 Page 2 0 0 0 1 1 Page 3 : : : : :: : : : : :: 1 1 1 1 0 Page 30 1 1 1 1 1 Page 31 User can use PAGE instruction to change page to maintain program page by user. Otherwise, user can use far jump (FJMP) or far call (FCALL) instructions to program user's code. And the program page is maintained by EMC's complier. It will change user's program by inserting instructions within program. Bit 5 ~ Bit 6(P55 ~ P57) : 3-bit PORT5(5~7) I/O data register User can use IOC register to define input or output each bit.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 16
8/23/04 (V1.5)
EM78871 8-bit Micro-controller PAGE1 (SPI data buffer)
7 6 5 4 3 2 1 0 SPIB7 SPIB6 SPIB5 SPIB4 SPIB3 SPIB2 SPIB1 SPIB0 Bit 0 ~ Bit 7 (SPIB0 ~ SPIB7) : SPI data buffer If you write data to this register, the data will write to SPIW register. If you read this data, it will read the data from SPIR register. Please refer to figure7
R6 (PORT6 I/O data) PAGE0 (PORT6 I/O data register)
7 6 5 4 3 P67 P66 P65 P64 P63 Bit 0 ~ Bit 7 (P60 ~ P67) : 8-bit PORT6(0~7) I/O data register User can use IOC register to define input or output each bit.. 2 P62 1 P61 0 P60
PAGE1 (Unused)
7 6 5 4 3 2 1 0
Bit 0 ~ Bit 7 : unused
R7 (PORT7 I/O data) PAGE0 (PORT7 I/O data register)
7 6 5 4 3 P77 P76 P75 P74 P73 Bit 0 ~ Bit 7 (P70 ~ P77) : 8-bit PORT7(0~7) I/O data register User can use IOC register to define input or output each bit. 2 P72 1 P71 0 P70
PAGE1 (Unused)
7 6 5 4 3 2 1 0
Bit 0 ~ Bit 7 : unused
R8 (PORT8 I/O data) PAGE0 (PORT8 I/O data register)
7 6 5 4 3 P87 P86 P85 P84 P83 Bit 0 ~ Bit 7 (P80 ~ P87) : 8-bit PORT8 ( 0~7 ) I/O data register User can use IOC register to define input or output each bit. 2 P82 1 P81 0 P80
PAGE1 (Unused)
7 6 5 4 3 2 1 0
Bit 0 ~ Bit 7 : unused
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 17
8/23/04 (V1.5)
EM78871 8-bit Micro-controller R9 (PORT9 I/O data, extra LCD address bit ) PAGE0 (PORT9 I/O data register)
7 6 5 4 3 P97 P96 P95 P94 P93 Bit 0 ~ Bit 7 (P90 ~ P97) : 8-bit PORT9 ( 0~7 ) I/O data register User can use IOC register to define input or output each bit. 2 P92 1 P91 0 P90
PAGE1 (LCD address MSB bit)
7 6 5 4 3 2 1 LCDA8 Bit 0 ~ Bit 6 : unused Bit 7 (LCDA8) : MSB of LCD address for LCD RAM reading or writing Other LCD address bits LCDA7 ~ LCDA0 are set from RA PAGE1 Bit 7 ~ Bit 0. For LCD address access over 0xFFH, set this bit to "1"; otherwise set this bit to "0". 0
RA (CPU power saving, PLL, Main clock selection, FSK, Watchdog timer, LCD address) PAGE0 (CPU power saving bit, PLL, Main clock selection bits, FSK , Watchdog timer enable bit)
7 6 5 4 3 2 1 0 SLEEP_N PLLEN CLK1 CLK0 FSKPWR FSKDATA /CD WDTEN Bit 0 (WDTEN) : Watch dog control register User can use WDTC instruction to clear watch dog counter. The counter 's clock source is 32768/2 Hz. If the prescaler assigns to TCC. Watch dog will time out by (1/32768 )*2 * 256 = 15.616ms. If the prescaler assigns to WDT, the time of time out will be more times depending on the ratio of prescaler. 0/1 disable/enable Bit 1 (/CD) : FSK carrier detect indication 0/1 Carrier Valid/Carrier Invalid It's a read only signal. If FSK decoder detect the energy of mark or space signal. The Carrier signal will go to low level. Otherwise it will go to high.. Note!! Should be at normal mode. Bit 2 (FSKDATA) : FSK decoding data output It's a read only signal. If FSK decode the mark or space signal , it will output high level signal or low level signal at this register. It's a raw data type. That means the decoder just decode the signal and has no process on FSK signal. Note!! Should be at normal mode. User can use FSK data falling edge interrupt function to help data decoding. Ex: MOV A,@01000000 IOW IOCF ;enable FSK interrupt function CLR RF ENI ;wait for FSK data's falling edge : 0 = Space data ( 2200Hz ) 1 = Mark data (1200Hz) Bit 3 (FSKPWR) : FSK power control 0/1 FSK decoder powered down / FSK decoder powered up It's the control register of FSK block power. For DTMF power up, be sure FSK powered down. (IOC9 PAGE1 bit7 set 1, this bit be set to 0)
The relation between bit 1 to bit 3 is shown in Fig.9. You have to power FSK decoder up first, then wait a setup time (Tsup) and check carrier signal (/CD). If the carrier is low, program can process the FSK data.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 18
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
FIRST RING 2 SECONDS TIP/RING /CD
0.5 SEC FSK signal Tcdl Tdoc
0.5 SEC
SECOND RING 2 SECONDS
Tcdh
FSKDATA DATA Tsup /FSKPWR
Fig.9 The relation between bit 1 ~ bit 3 The controller is a CMOS device designed to support the Caller Number Deliver feature which is offered by the Regional Bell Operating Companies. The FSK block comprises one path: the signal path. The signal path consist of an input differential buffer, a band pass filter, an FSK demodulator and a data valid with carrier detect circuit. In a typical application, user can use his own external ring detect output as a triggering input to IO port. User can use this signal to wake up whole chip by external ring detect signal. By setting "1" to bit 3 (FSKPWR) of register RA to activate the block of FSK decoder. If bit 3 (FSKPWR) of register RA is set to "0", the block of FSK decoder will be powered down. The input buffer accepts a differential AC coupled input signal through the TIP and RING input and feeds this signal to a band pass filter. Once the signal is filtered, the FSK demodulator decodes the information and sends it to a post filter. The output data is then made available at bit 2 (FSKDATA) of register RA. This data, as sent by the central office, includes the header information (alternate "1" and "0") and 150 ms of marking which precedes the date, time and calling number. If no data is present, the bit 2 (DATA) of register RA is held on "1" state. This is accomplished by an carrier detect circuit which determines if the in-band energy is high enough. If the incoming signal is valid, bit 1 (/CD) of register RA will be "0" otherwise it will be held on "1". And thus the demodulated data is transferred to bit 2 (DATA) of register RA. If it is not, then the FSK demodulator is blocked. Bit 4 ~ Bit 5 (CLK0 ~ CLK1) : Main clock selection bits User can choose different frequency of main clock by CLK1 and CLK2. All the clock selection is list below. PLLEN 1 1 1 1 0 0 0 0 CLK1 0 0 1 1 Don't care Don't care Don't care Don't care CLK0 0 1 0 1 don't care don't care don't care don't care Sub clock 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz 32.768kHz MAIN clock CPU clock
895.658kHz 895.658kHz (Normal mode) 1.7913MHz 1.7913MHz (Normal mode) 10.7479MHz 10.7479MHz (Normal mode) 3.5826MHz 3.5826MHz (Normal mode) Don't care 32.768kHz (Green mode) Don't care 32.768kHz (Green mode) Don't care 32.768kHz (Green mode) Don't care 32.768kHz (Green mode)
Bit 6 (PLLEN) : PLL enable control bit It is CPU mode control register. If PLL is enabled, CPU will operate at normal mode (high frequency, main clock); otherwise, it will run at green mode (low frequency, 32768 Hz). 0/1 disable/enable
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 19
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
3.5826M Hz to analog circuit
PLL
/ / x x
4 =>895.658kHz 2 =>1.7913M Hz 1 =>3.5826M Hz 3 =>10.7479M Hz
1 switch System clock 0
Sub-clock 32.768kHz
ENPLL CLK1 ~ CLK0
Fig.10 The relation between 32.768kHz and PLL Bit 7(SLEEP_N) : Power saving mode control register When PLL is disabled, user can set this bit after using "SLEP" instruction for SLEEP mode or IDLE mode selection 0 SLEEP mode 1 Don't allowed this setting This bit will decide SLEP instruction which mode to go. The status after wake-up and the wake-up sources list as the table below. Wakeup signal SLEEP mode GREEN mode NORMAL mode RA(7,6)=(0,0) RA(7,6)=(x,0) RA(7,6)=(x,1) + SLEP no SLEP no SLEP TCC time out No function Interrupt Interrupt IOCF bit 0=1 (jump to address 8 (jump to address And "ENI" at page0) 8 at page0) COUNTER1 time out IOCF bit 1=1 And "ENI" COUNTER2 time out IOCF bit 2=1 And "ENI" WDT time out Interrupt (jump to address 8 at page0) No function Interrupt (jump to address 8 at page0) RESET and RESET and Jump Jump to address to address 0 0 RESET and Interrupt Jump to address (jump to address 8 0 at page0) No function Interrupt (jump to address 8 at page0) Interrupt (jump to address 8 at page0) RESET and Jump to address 0 Interrupt (jump to address 8 at page0)
PORT7 IOCF bit3 or bit4 or bit5 = 1 And "ENI"
No function Interrupt Interrupt IOCE page2 bit 6 = 1 (jump to address 8 (jump to address And RE page1 bit6 at page0) 8 at page0) logic level variation (switch by EDGE bit) And "ENI" Stack overflow No function Interrupt Interrupt IOC5 page2 bit7=1 (jump to address 8 (jump to address &bit 6: 0 1 at page0) 8 at page0) And "ENI" Stack overflow interrupt function is exist in ROM less and OTP chip only. PORT70 ~ PORT73 's wakeup function is controlled by IOCF bit3 and ENI instruction. They are falling edge trigger. PORT74 ~ PORT76 's wakeup function is controlled by IOCF bit4 and ENI instruction. They are falling edge trigger.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 20
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
PORT77 's wakeup function is controlled by IOCF bit5 and ENI instruction. It's falling edge or rising edge trigger (controlled by CONT register).
PAGE1 (LCD address)
7 6 5 4 3 2 1 0 LCDA7 LCDA6 LCDA5 LCDA 4 LCDA 3 LCDA 2 LCDA 1 LCDA 0 Bit 0 ~ Bit 7 (LCDA0 ~ LCDA7) : LCD address for LCD RAM reading or writing The data in the LCD RAM correspond to the COMMON and SEGMENT signals as the table . COM23 ~ COM16 (set R9 PAGE1 bit7=1) Address 100H Address 101H Address 102H : : : Address 14EH Address 14FH Address 150H : Address 17FH COM15 ~COM8 (set R9 PAGE1 bit7=0) Address 80H Address 81H Address 82H : : : Address CEH Address CFH Address D0H : Address FFH COM7 ~ COM0 (set R9 PAGE1 bit7=0) Address 00H Address 01H Address 02H : : : Address 4EH Address 4FH Address 50H : Address 7FH
SEG0 SEG1 SEG1 : : : SEG78 SEG79 Empty : Empty
RB (PORTB I/O data, LCD data) PAGE0 (PORTB I/O data register)
7 6 5 4 3 PB7 PB6 PB5 PB4 PB3 Bit 0 ~ Bit 7 (PB0 ~ PB7) : 8-bit PORTB(0~7) I/O data register User can use IOC register to define input or output each bit. 2 PB2 1 PB1 0 PB0
PAGE1 (LCD data buffer)
7 6 5 4 3 2 1 LCDD7 LCDD6 LCDD5 LCDD4 LCDD3 LCDD2 LCDD1 Bit 0 ~ Bit 7 (LCDD0 ~ LCDD7) : LCD data buffer for LCD RAM reading or writing 0 LCDD0
Example. MOV MOV MOV MOV MOV MOV :
A,@0 R9_PAGE1,A RA_PAGE1,A A,@0XAA RB_PAGE1,A A,RB_PAGE1
;ADDRESS ;WRITE DATA 0XAA TO LCD RAM ;READ DATA FROM LCD RAM
RC (PORTC I/O data, Data RAM data) PAGE0 (PORTC I/O data register)
7 6 5 4 3 PC7 PC6 PC5 PC4 PC3 Bit 0 ~ Bit 7 (PC0 ~ PC7) : 8-bit PORTC(0~7) I/O data register User can use IOC register to define input or output each bit. 2 PC2 1 PC1 0 PC0
PAGE1 (Data RAM data buffer)
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 21
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
7 6 5 4 3 2 1 0 RAMD7 RAMD6 RAMD5 RAMD4 RAMD3 RAMD2 RAMD1 RAMD0 Bit 0 ~ Bit 7 (RAMD0 ~ RAMD7) : Data RAM data buffer for RAM reading or writing. Ex. MOV A , @1 MOV RD_PAGE1 , A MOV A , @0 MOV RE_PAGE1 , A MOV A , @0x55 MOV RC_PAGE1 , A ;write data 0x55 to DATA RAM which address is "0001". MOV A , RC_PAGE1 ;read data :
RD (Comparator control, Data RAM address(0 ~ 7)) PAGE0 (Comparator control bits)
7 6 5 4 3 2 1 0 CMPEN CMPFLAG CMPS1 CMPS0 CMP_B3 CMP_B2 CMP_B1 CMP_B0 If user define PORT63 , PORT64 or PORT65 (by CMPIN1, CMPIN2, CMPIN3 at IOCE page1) as a comparator input or PORT6. User can use this register to control comparator's function. Bit 0~Bit 3(CMP_B0~CMP_B3) : Reference voltage selection of internal bias circuit for comparator. Reference voltage for comparator = VDD x ( n + 0.5 )/ 16 , n = 0 to 15 Bit 4~Bit 5(CMPS0~CMPS1) : Channel selection from CMP1 to CMP3 for comparator CMPS1 CMPS0 Input 0 0 CMP1 0 1 CMP2 1 0 CMP3 1 1 Reserved Bit 6(CMPFALG) : Comparator output flag 0 Input voltage < reference voltage 1 Input voltage > reference voltage Bit 7(CMPEN) : Enable control bit of comparator. 0/1 disable/enable, When this bit is set to "0", 2.0V ref circuit is also powered off.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 22
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
CMP1 MUX PORT63
P63/CM P1
CM PIN1 P64/CM P2 CMP2 MUX MUX PORT64 CM PIN2 P65/CM P3 CMP3 MUX PORT65 2 CMPS1 CMPS0 1 0 M UX
+
CMPFLAG
CM PIN3
VDD
V2_0 ref. CMPEN
2.0V
MUX
VR
CMPREF CM PEN 1/2R 1111 R 1110 R M UX
VRSEL
0000 1/2R 4 CMP_B3 to CMP_B0
Fig.11 Comparator circuit
CMPEN
CMP1 to CMP3 reference voltage
Setup time 10us
CPU clock
CMPFLAG
Compare start
Compare end
Fig.12 Comparator timing
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 23
8/23/04 (V1.5)
EM78871 8-bit Micro-controller PAGE1 (Data RAM address0 ~ address7)
7 6 5 4 3 2 1 0 RAMA7 RAMA6 RAMA5 RAMA4 RAMA3 RAMA2 RAMA1 RAMA0 Bit 0~Bit 7(RAMA0~RAMA7) : Data RAM address (address0 to address7) for RAM reading or writing
RE (CAS, Key scan, LCD control, Data RAM address(8 ~ 11)) PAGE0 (Key scan control, LCD control)
7 6 5 4 3 2 1 0 CAS KEYCHK KEYSTRB KEYSCAN LCD1 LCD0 LCDM1 LCDM0 Bit 0~Bit 1(LCDM0~LCDM1) : LCD common mode, bias select and COM/SEG switch control bits LCDM1, LCDM0 COM output mode LCD bias COM/SEG switch 0,0 16 common 1/4 bias SEG0 ~ SEG7 select 0,1 9 common 1/4 bias SEG0 ~ SEG7 select 1,0 8 common 1/4 bias SEG0 ~ SEG7 select 1,1 24 common 1/5 bias COM16 ~ COM23 select When 8, 9 and 16 LCD common mode is set, COM16/SEG0 pin ~ COM23/SEG7 pin are also set to SEG0 ~ SEG7 and LCD bias is 1/4 bias. When 24 LCD common mode is set, COM16/SEG0 pin ~ COM23/SEG7 pin are also set to COM16 ~ COM23 and LCD bias is 1/5 bias. Bit 2~Bit 3 (LCD0~LCD1) : LCD operation function definition. LCD1, LCD0 LCD operation 0,0 Disable 0,1 Blanking 1,0 Reserved 1,1 LCD enable Key strobe and Key check functions should be normal operating whenever LCD is enabled or disabled. The controller can drive LCD directly. LCD block is made up of LCD driver, display RAM, segment output pins, common output pins and LCD operating bias pins. Duty, the number of segment , the number of common and frame frequency are determined by LCD mode register RE PAGE0 Bit 0~ Bit 1. When 8, 9 or 16 LCD commons are used, LCD operating bias pins VC1, VC2, VC4 and VC5 need to be connected 0.1uF capacitors to the ground (VC3 is not necessary). When 24 LCD common is used, all LCD operating bias pins VC1 ~ VC5 need to be connected 0.1uF capacitors to the ground. LCD driver can be controlled as different driving ability (refer to IOC6 PAGE1 Option-B register). The basic structure contains a timing control which uses the basic frequency 32.768kHz to generate the proper timing for different duty and display access. RE PAGE1 register is a command register for LCD driver and display. The LCD display (disable, enable, blanking) is controlled by RE PAGE0 Bit 2 ~ Bit 3 and the driving duty is decided by RE PAGE Bit 0 ~ Bit 2. LCD display data is stored in data RAM which address and data access controlled by registers R9, RA PAGE1 and RB PAGE1. User can regulate the contrast of LCD display by IOC5 PAGE1 (BIAS3..BIAS0). Up to 16 levels contrast is convenient for better display. And the internal voltage follower can afford large driving source. COM signal : The number of COM pins varies according to the duty cycle used, as following: In 1/8 duty mode COM8 ~ COM15 must be open. In 1/9 duty mode COM9~ COM15 must be open In 1/16 duty mode COM0 ~ COM15 pins must be used. In 1/24 duty mode COM0 ~ COM23 pins must be used.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 24
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
duty COM0 ~ COM7 1/8 o 1/9 o 1/16 o 1/24 o x : open, o : select COM8 COM9 X x O x O o O o .. .. .. .. .. COM15 COM15 ~ COM23 x x x x o x o o
SEG signal : The segment signal pins are connected to the corresponding display RAM. The high byte to the low byte Bit 0 ~ Bit 7 are correlated to COM0 ~ COM23 respectively . When a bit of display RAM is 1, a select signal is sent to the corresponding segment pin, and when the bit is 0 , a non-select signal is sent to the corresponding segment pin. Bit 4(KEYSCAN) : Key scan function enable control bit 0/1 disable/enable If you enable key scan function LCD waveform will has a small pulse within a period like Fig.13.
COM2
V1 V2 V4 V5 GND
SEG
V1 V2 V4 V5 GND
V1 V2 V4 V5
30us
GND
Fig.13. key scan waveform for 1/8, 1/9, 1/16 duty Bit 5(KEYSTRB) : Key strobe enable control bit 0/1 disable/enable key strobe signal , if you set this bit , segment will switch to strobe signal temporally and output zero signal ( one instruction long ) one by one from segment 8 to segment 23. During one segment strobe time, CPU will check port7(0:3) equal to "1111" or not. If not, CPU will latch a zero at IOC7 PAGE1 and IOC8 PAGE1 one by one depends on which segment strobe. After strobe, this bit will be cleared . Fig.14 is key strobe signal.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 25
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
One instruction
REGISTER IOC7(0) IOC7(1) IOC7(2) IOC7(3) IOC7(4) IOC7(5) IOC7(6) IOC7(7) IOC8(0) IOC8(1) IOC8(2) IOC8(3) IOC8(4) IOC8(5) IOC8(6) IOC8(7)
STROBE SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Fig.14 key strobe signal Bit 6(KEYCHK) : Key check enable control bit 0 disable key check function. 1 enable key check function. SEG8 to SEG23 will keep low level. Figure 15 is relationship between KEYSCAN, KEYSTROBE , KETCHECK and segments. And figure 16 is key scan flow by interrupt trigger.
RELATION BETWEEN S(8:23) , KEYSCAN, KEY STROBE, KEY CHECK
KEY SCAN PULSE
KEY SCAN CONTROL
0
SEGMENT(8:23) KEY STROBE SIGNAL
MUX
1
0 GND
1
MUX
KEYSTROBE
KEYCHECK
Fig.15 KEYSCAN, KEYSTROBE , KEYCHECK and segments. Bit 7(CAS) : CALL WAITING decoding output 0/1 CW data valid / No data
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 26
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
Set port7(3:0) input (IOC7 (7:0) = " 0x0f " ) set IOC page1 (BS R3,IOC_PAGE) port7 pull high (IOCA=0x0f) set IOC page0 (BC R3,IOC_PAGE) enable key scan signal (RE bit4=1) set INT0 interrupt ENI
N Interrupt occur?
Y Enable main clock (Normal mode) program delay enable RE(6) key check Read port7 ( column key ) disable RE(6) key check set strobe function enable RE (5) keystrobe program delay read IOC7,IOC8 (row key)
Execution key function
Get the key location
Fig.16 key scan flow by interrupt trigger
PAGE1 (Data RAM address8 ~ address11)
3 2 1 0 RAMA11 RAMA10 RAMA9 RAMA8 Bit 0~Bit 3(RAMA8~RAMA11) : Data RAM address (address8 to address11) for RAM reading. Bit 4~Bit5 : unused Bit 6:unused Bit 7 :unused 7 6 5 4
RF (Interrupt flags)
7 6 5 4 3 2 1 0 RBF/SDT FSK/CW INT2 INT1 INT0 CNT2 CNT1 TCIF "1" means interrupt request, "0" means non-interrupt Bit 0(TCIF) : TCC timer overflow interrupt flag Set when TCC timer overflows . Bit 1(CNT1) : Counter1 timer overflow interrupt flag Set when counter1 timer overflows. Bit 2(CNT2) : Counter2 timer overflow interrupt flag Set when counter2 timer overflows . Bit 3(INT0) : External INT0 pin interrupt flag If PORT70 ,PORT71,PORT72 or PORT73 has a falling edge trigger signal. CPU will set this bit.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 27
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
Bit 4(INT1) : External INT1 pin interrupt flag If PORT74 ,PORT75 or PORT76 has a falling edge trigger signal. CPU will set this bit. Bit 5(INT2) : External INT2 pin interrupt flag If PORT77 has a falling edge or rising edge (controlled by CONT register) trigger signal. CPU will set this bit. Bit 6(FSK/CW) : FSK data or Call waiting data interrupt flag. If FSKDATA or CAS has a falling edge trigger signal, CPU will set this bit. Bit 7( RBF/STD) : SPI data transfer complete or DTMF receiver signal valid interrupt If serial IO 's RBF signal has a rising edge signal (RBF set to "1" when transfer data completely), CPU will set this bit. Or DTMF receiver's STD signal has a rising edge signal (DTMF decode a DTMF signal). IOCF is the interrupt mask register. User can read and clear. Trigger edge as the table Signal Trigger TCC Time out COUNTER1 Time out COUNTER2 Time out INT0 Falling edge INT1 Falling edge INT2 Falling/Falling & rising edge Controlled by CONT register FSK Falling edge RBF/STD Rising edge
R10~R3F (General Purpose Register)
R10~R3F (Banks 0 ~ 3) : All of them are general purpose registers.
VII.2 Special Purpose Registers
A (Accumulator)
Internal data transfer, or instruction operand holding It's not an addressable register.
CONT (Control Register)
7 6 5 4 INT_EDGE INT TS Bit 0~Bit 2(PSR0~PSR2) : TCC/WDT prescaler bits PSR2 PSR1 PSR0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Bit 3(PAB) : Prescaler assignment bit 0/1 TCC/WDT Bit 4 : unused 3 PAB 2 PSR2 1 PSR1 0 PSR0
TCC rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
WDT rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
Bit 5(TS) : TCC signal source 0 Instruction clock 1 16.384kHz Instruction clock = MCU clock/2, Refer to RA Bit 4 ~ Bit 6 for PLL and Main clock selection. See fg.17.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 28
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
Bit 6(INT) : INT enable flag 0 interrupt masked by DISI or hardware interrupt 1 interrupt enabled by ENI/RETI instructions Bit 7(INT_EDGE) : interrupt edge type of P77 0 77 's interruption source is a rising edge signal and falling edge signal. 1 P77 's interruption source is a falling edge signal. CONT register is readable (CONTR) and writable (CONTW). TCC and WDT : There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only or WDT only at the same time. An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT register. See the prescaler ratio in CONT register. Fig.16 depicts the circuit diagram of TCC/WDT. Both TCC and prescaler will be cleared by instructions which write to TCC each time. The prescaler will be cleared by the WDTC and SLEP instructions, when assigned to WDT mode. The prescaler will not be cleared by SLEP instructions, when assigned to TCC mode.
Data Bus
Instruction clock 16.384kHz
M U X
M U X
PAB
SYNC 2 cycles
TCC(R1)
TS
TCC overflow interrupt
W DT
WDTE
M U X
PAB
8-bit Counter
PSR0 ~ PSR2
8-to-1 MUX
MUX
PAB
WDT timeout
Fig.17 Block diagram of TCC WDT
IOC5 (PORT5 I/O control, PORT switch, Key tone, CDAS, LCD bias) PAGE0 (PORT5 I/O control register, PORT switch)
7 6 5
IOC57
IOC56
IOC55
4 CASPWR
3 P9SH
2 P9SL
1 P8SH
0 P8SL
Bit 0 (P8SL) : Switch low nibble I/O PORT8 or LCD segment output for share pins SEGxx/P8x pins 0 select normal P80 ~ P83 for low nibble PORT8 1 select SEG64 ~ SEG67 output for LCD SEGMENT output. Bit 1 (P8SH) : Switch high nibble I/O PORT8 or LCD segment output for share pins SEGxx/P8x pins 0 select normal P84 ~ P87 for high nibble PORT8 1 select SEG68 ~ SEG71 output for LCD SEGMENT output. Bit 2 (P9SL) : Switch low nibble I/O PORT9 or LCD segment output for share pins SEGxx/P9x pins 0 select normal P90 ~ P93 for low nibble PORT9
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 29
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
1 select SEG72 ~ SEG75 output for LCD SEGMENT output. Bit 3 (P9SH) : Switch high nibble I/O PORT9 or LCD segment output for share pins SEGxx/P9x pins 0 select normal P94 ~ P97 for high nibble PORT9 1 select SEG76 ~ SEG79 output for LCD SEGMENT output.*Bit 4:general register Bit 4 (CWPWR) : Power control of Call Waiting circuit 1/0 enable circuit /disable circuit Bit 5~Bit 6(IOC55~IOC57) : PORT5 I/O direction control registers. 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance
PAGE1 (Key tone control, CDAS, LCD bias control)
7 6 5 4 3 KT1 KT0 KTS CDAS BIAS3 Bit 0~Bit 3(BIAS0~BIAS3) : LCD operation voltage selection V1 = VDD * (5 - n/15)/5 (BIAS3 to BIAS0) 0000 0001 0010 0011 0100 : 1101 1110 1111 V1 voltage VDD * (5-0/15)/5 VDD * (5-1/15)/5 VDD * (5-2/15)/5 VDD * (5-3/15)/5 VDD * (5-4/15)/5 : VDD * (5-13/15)/5 VDD * (5-14/15)/5 VDD * (5-15/15)/5 2 BIAS2 1 BIAS1 0 BIAS0
Example (VDD=5V) 5V 4.93V 4.86V 4.80V 4.73V : 4.13V 4.07V 4.0V
COMs BIAS MUX VC1 ~ VC5 generator LCD driver for COM and SEG SEGs
4
BIAS3 to BIAS0 VC1 ~ VC5
Fig.18 The relation between bias and V1 to V5
Fig.19a LCD waveform (1/4 bias) for 1/8 duty, 1/9 duty, 1/16 duty
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 30
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
FRAME
V1 V2 V4 V5 GND V1 V2 V4 V5 GND V1 V2 V4 V5 GND V1 V2 V4 V5 GND
COM0 COM1
COM2
SEG
dark
SEG
light
V1 V2 V4 V5 GND
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 31
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
frame
V1 v2 v3 v4 v5 Gnd V1 v2 v3 v4 v5 Gnd V1 v2 v3 v4 v5 Gnd
com0
com1
com2
seg
V1 v2 v3 v4 v5 Gnd
dark
V1 v2 v3 v4 v5 Gnd
seg
light
Fig.19b LCD waveform (1/5 bias) for 1/24 duty
Bit 4(CDAS) : Current DA switch 0 normal PORT66 1 Current DA output Bit 5(KTS) : Key tone output switch 0 normal PORT67 1 key tone output . Bit 6~Bit 7(KT0~KT1) : Key tone output frequency and its power control KT1 0 0 1 1 KT0 0 1 0 1 Key tone frequency and power 32.768KHz/32 = 1.024kHz clock and enable 32.768KHz/16 = 2.048kHz clock and enable 32.768KHz/8 = 4.096kHz clock and enable Power off key tone
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 32
8/23/04 (V1.5)
EM78871 8-bit Micro-controller IOC6 (PORT6 I/O control, CDA, PORT switch, LCD driving control) PAGE0 (PORT6 I/O control register)
7 6 5 4 3 2 IOC67 IOC66 IOC65 IOC64 IOC63 IOC62 Bit 0~Bit 7(IOC60~IOC67) : PORT6(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance 1 IOC61 0 IOC60
PAGE1 (Current DA control,)
7 6 5 4 3 2 1 0
DAEN
DA6
DA5
DA4
DA3
DA2
DA1
DA0
Bit 0~Bit 6(DA0~DA6) : Current DA output buffer User can use this buffer to control the output current of current DA for the driving transistor of speaker. Bit 7 (DAEN) : Current DA enable control 0/1 disable/enable
DA6..DA0
VDD
current DA circuit
DAOUT PORT66 PORT66 MUX
DAEN DAS
Fig.20 Current DA structure
PAGE 2 (PORT switch, LCD driving ability control)
7 6 5 4 3 PCSH PCSL PBS LCDDV1 LCDDV0 Bit 0~Bit 2(DAL0~DAL1) : change output level of current DA CDAL2 0 0 0 0 1 1 1 1 CDAL1 0 0 1 1 0 0 1 1 CDAL0 0 1 0 1 0 1 0 1 2 CDAL2 1 CDAL1 0 CDAL0
Output level L0 (ratio = 1/8) L1 (ratio = 2/8) L2 (ratio = 3/8) L3 (ratio = 4/8) L4 (ratio = 5/8) L5 (ratio = 6/8) L6 (ratio = 7/8) L7 (ratio =1)
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 33
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
Bit 3~Bit 4(LCDDV0~LCDDV1) : LCD driver's driving ability control LCDDV1 0 0 1 1 LCDDV0 0 1 0 1 Driving mode Normal mode (ratio = 1) Weak mode (ratio = 1/2) Strong mode (ratio = 2) Maximum mode (ratio = 4)
LCDDV0 ~ LCDDV1 are used to select the driving ability of LCD driver. The driving ability is Maximum mode > Strong mode > Normal mode > Weak mode by 1/2 ratio individually. The larger driving ability it is selected, the larger output loading of LCD driver output can be afforded and the more current consumption is occurred. It depends on user's application. Bit 5(PBS) : Switch I/O PORTB or LCD segment output for share pins SEGxx/PBx 0 select normal PB0 ~ PB7 for PORTB 1 select SEG48 ~ SEG55 output for LCD SEGMENT output. Bit 6(PCSL) : Switch low nibble I/O PORTC or LCD segment output for share pins SEGxx/PCx 0 select normal PC0 ~ PC3 for low nibble PORTC 1 select SEG56 ~ SEG59 output for LCD SEGMENT output. Bit 7(PCSH) : Switch high nibble I/O PORTC or LCD segment output for share pins SEGxx/PCx 0 select normal PC4 ~ PC7 for high nibble PORTC 1 select SEG60 ~ SEG63 output for LCD SEGMENT output.
IOC7 (PORT7 I/O control, Key strobe(8~15)) PAGE0 (PORT7 I/O control register)
7 6 5 4 3 2 IOC77 IOC76 IOC75 IOC74 IOC73 IOC72 Bit 0~Bit 7(IOC70~IOC77) : PORT7(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance 1 IOC71 0 IOC70
PAGE1 (Key strobe control register)
7 6 5 4 3 2 1 0
STRB15
STRB14
STRB13
STRB12
STRB11
STRB10
STRB9
STRB8
Bit 0~Bit 7(STRB8~STRB15) : Key strobe control bits These key strobe control registers correspond to SEGMENT8 to SEGMENT15. Please refer KEYSTOBE explanation (RE page0).
IOC8 (PORT8 I/O control, , Key strobe(16~23)) PAGE0 (PORT8 I/O control register)
7 6 5 4 3 2 IOC87 IOC86 IOC85 IOC84 IOC83 IOC82 Bit 0~Bit 7(IOC80~IOC87) : PORT8(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance 1 IOC81 0 IOC80
PAGE1 (Key strobe control register)
7 6 5 4 3 2 1 0
STRB23
STRB22
STRB21
STRB20
STRB19
STRB18
STRB17
STRB16
Bit 0~Bit 7(STRB16~STRB23) : Key strobe control bits These key strobe control registers correspond to SEGMENT16 to SEGMENT23. Please refer KEYSTOBE explanation (RE page0).
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 34
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
IOC9 (PORT9 I/O control, DTMF receiver) PAGE0 (PORT9 I/O control register)
7 6 5 4 3 2 IOC97 IOC96 IOC95 IOC94 IOC93 IOC92 Bit 0~Bit 7(IOC90~IOC97) : PORT9(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance 1 IOC91 0 IOC90
PAGE1 (DTMF receiver)
7 6 5 4 3 2 1 0 DREN STD TDP2 TDP1 Q4 Q3 Q2 Q1 Bit 0~Bit 3(Q1~Q4) : DTMF receiver decoding data To provide the code corresponding to the last valid tone-pair received (see code table). STD signal which steering output presents a logic high when a received tone-pair has been registered and the Q4 ~ Q1 output latch updated and generate a interruption (IOCF has enabled); returns to logic low when the voltage on ST/GT falls below Vtst.
F low 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 Any
F high 1209 1336 1477 1209 1336 1477 1209 1336 1477 1209 1336 1477 1633 1633 1633 1633 Any
Key 1 2 3 4 5 6 7 8 9 0 * # A B C D Any
DREN 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Q4~Q1 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000 xxxx (x:unknown)
Bit 4~Bit 5(TDP1~TDP2) : Tone detection present time setup. TDP2 0 0 1 1 TDP1 0 1 0 1 Tdp 20 ms 15 ms 10 ms 5 ms
Bit 6(STD) : Delayed steering output. Presents a logic high when a received tone-pair has been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below V tst.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 35
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
0/1 Data invalid/data valid Bit 7(DREN) : DTMF receiver power control 0/1 power down/ power up Be sure open main clock before using DTMF receiver circuit and shut down FSK power (R9 PAGE0 bit 3 set 0). A logic low applied to DREN will shut down power of the device to minimize the power consumption in a standby mode. It stops functions of the filters. In many situations not requiring independent selection of receive and pause, the simple steering circuit of is applicable. Component values are chosen according to the following formulae: t REC = t DP + t GTP t ID = t DA + t GTA The value of t DP is a parameter of the device and t REC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1 uF is recommended for most applications, leaving R to be selected by the designer. For example, a suitable value of R for a t REC of 30mS would be 300k. Different steering arrangements may be used to select independently the guard-times for tone-present (t GTP ) and tone-absent (t GTA ). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and inter digital pause. Guard-time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Increasing t REC improves talk-off performance, since it reduces the probability that tones simulated by speech will maintain signal condition for long enough to be registered. On the other hand, a relatively short t REC with a long t DO would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop-outs would be required.
VDD
VDD C ST/GT EST R
Fig.21. DTMF receiver delay time control
TONE Tdp 5~20mS by S/W Tgtp 30mS Typ. ST/GT
TONE Tgta 30mS Typ.
EST
Vtst 1/2 VDD Tpq 8 uS Typ.
Q4..Q1
STD
LINE_ENG
Fig.22. DTMF receiver timing.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 36
8/23/04 (V1.5)
EM78871 8-bit Micro-controller IOCA (CN1's and CN2's clock and scaling, PORT7 pull high control) PAGE0 (Counter1's and Counter2's clock and scale setting)
7 6 5 4 CNT2S C2P2 C2P1 C2P0 Bit 0~Bit 2(C1P0~C1P2) : Counter1 scaling C1P2 C1P1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Bit 3(CNT1S) : Counter1 clock source 0/1 16.384kHz/instruction clock Bit 4~Bit 6(C2P0~C2P2) : Counter2 scaling C2P2 C2P1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 Bit 7(CNT2S) : Counter2 clock source 0/1 16.384kHz/instruction clock C1P0 0 1 0 1 0 1 0 1 3 CNT1S 2 C1P2 1 C1P1 0 C1P0
COUNTER1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
C2P0 0 1 0 1 0 1 0 1
COUNTER2 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256
PAGE1 (PORT7 pull high control register)
7 6 5 4 3 PH77 PH76 PH75 PH74 PH73 Bit 0~Bit 7(PH70~PH77) : PORT7(0~7) pull high control register 0 disable pull high function. 1 enable pull high function 2 PH72 1 PH71 0 PH70
IOCB (PORTB I/O control, PORT6 pull high control) PAGE0 (PORTB I/O control register)
7 6 5 4 3 2 IOCB7 IOCB6 IOCB5 IOCB4 IOCB3 IOCB2 Bit 0~Bit 7(IOCB0~IOCB7) : PORTB(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance 1 IOCB1 0 IOCB0
PAGE1 (PORT6 pull high control register)
7 6 5 4 3 PH67 PH66 PH65 PH64 PH63 Bit 0~Bit 7(PH60~PH67) : PORT6(0~7) pull high control register 0 disable pull high function. 1 enable pull high function * This specification is subject to be changed without notice. 37 2 PH62 1 PH61 0 PH60
__________________________________________________________________________________________________________________________________________________________________
8/23/04 (V1.5)
EM78871 8-bit Micro-controller IOCC (PORTC I/O control, TONE1 control) PAGE0 (PORT9 I/O control register)
7 6 5 4 3 2 IOCC7 IOCC6 IOCC5 IOCC4 IOCC3 IOCC2 Bit 0~Bit 7(IOCC0~IOCC7) : PORTC(0~7) I/O direction control register 0 put the relative I/O pin as output 1 put the relative I/O pin into high impedance 1 IOCC1 0 IOCC0
PAGE1 (TONE1 control register)
7 6 5 4 3 2 1 0
T17
T16
T15
T14
T13
T12
T11
T10
Bit 0~Bit 7(T10~T17) : Tone generator1`s frequency divider and power control Please Run in Normal mode . Clock source = 111957Hz T17~T10 = `11111111' Tone generator1 will has 439(111957/N , N=255) Hz SIN wave output. : : T17~T10 = `00000010' Tone generator1 will has 55978(111957/N , N=2) Hz SIN wave output. T17~T10 = `00000001' DC bias voltage output T17~T10 = `00000000' Power off Built-in tone generator can generate dialing tone signals for telephone of dialing tone type or just a single tone. In DTMF application, there are two kinds of tone. One is the group of row frequency (TONE1), the other is the group of column frequency (TONE2), each group has 4 kinds of frequency, user can get 16 kinds of DTMF frequency totally. Tone generator contains a row frequency sine wave generator for generating the DTMF signal which selected by IOCC page1 and a column frequency sine wave generator for generating the DTMF signal which selected by IOCD page1. This block can generate single tone by filling one of these two register. If all the values are low, the power of tone generators will turn off . TONE2 (IOCD PAGE1) High group freq. 1203.8Hz 1332.8Hz 1473.1Hz 1646.4Hz (0X5D) (0X54) (0X4C) (0X44) TONE1(IOCC page1) 699.7Hz(0x0A0) 1 2 3 A 772.1Hz(0x091) 4 5 6 B Low group freq. 854.6Hz(0x083) 7 8 9 C 940.8Hz(0x077) * 0 # D Also TONE1 and TONE2 are an asynchronous tone generator so the both can be used to generate Caller ID FSK signal. In FSK generator application, TONE1 or TONE2 can generate 1200Hz Mark bit and 2200Hz Space bit for Bell202 or 1300Hz Mark bit and 2100Hz Space bit for V.23. See the following table. TONE1(IOCC PAGE1) or Freq. (Hz) meaning TONE2(IOCD PAGE1) 0x5D 1203.8 Bell202 FSK Mark bit 0x33 2195.2 Bell202 FSK Space bit 0x56 1301.8 V.23 FSK Mark bit 0x35 2112.4 V.23 FSK Space bit
IOCD (Counter1 data, TONE2 control) PAGE0 (Counter1 data buffer)
7 6 5 4 3 2 1 0
CN17
CN16
CN15
CN14
CN13
CN12
CN11
CN10
Bit 0~Bit 7(CN10~CN17) : Counter1's data buffer
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 38
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
User can read and write this buffer. Counter1 is a eight bit up-counter with 8-bit prescaler that user can use IOCD to preset and read the counter. ( write = preset) After a interruption, it will reload the preset value. Example: write: IOW 0x0D ; write the data at accumulator to counter1 (preset) Example: read: IOR 0x0D ;read IOCD data and write to accumulator
PAGE1 (TONE2 control register)
7 6 5 4 3 2 1 0
T27
T26
T25
T24
T23
T22
T21
T20
Bit 0~Bit 7(T20~T27) : Tone generator1`s frequency divider and power control. Please refer to IOCC page1 Tone1 control register for detail.
IOCE (Counter2 data, Comparator and OP control , Energy Detector ) PAGE0 (Counter2 data buffer)
7 6 5 4 3 2 1 0
CN27
CN26
CN25
CN24
CN23
CN22
CN21
CN20
Bit 0~Bit 7(CN20~CN27) : Counter2's data buffer User can read and write this buffer. Counter2 is a eight bit up-counter with 8-bit prescaler that user can use IOCD to preset and read the counter. ( write = preset) After a interruption, it will reload the preset value. Example: write: IOW 0x0E ; write the data at accumulator to counter2 (preset) Example: read: IOR 0x0E ;read IOCE data and write to accumulator
PAGE1 (Comparator reference voltage type, PORT switch)
7 6 CMPREF CMPIN3 Bit 0 : unused Bit 1 : unused Bit 2~Bit 3 (P5S1~P5S2) : PORT5 switch P5S2 P5S1 PORT55 0 or 1 0 PORT55 0 or 1 1 STGT 5 CMPIN2 4 CMPIN1 3 P5S2 2 P5S1 1 0
PORT56 PORT56 EST
Status Normal PORT5 IO DTMF receiver IO
External reference signal The analog signal that is presented at Cin- compares to the signal at Cin+, and the digital output of the comparator is adjusted accordingly. *The reference signal must be between Vss and Vdd. *Threshold detector applications may be the same reference. *The comparator can operate from the same or different reference source Bit 4 (CMPIN1) : Switch for controlling PORT63 as IO PORT or a comparator input. 0 IO PORT63 1 comparator input Bit5 (CMPIN2) : Switch for controlling PORT64 as IO PORT or a comparator input. 0 IO PORT64 1 comparator input Bit 6 (CMPIN3) : Switch for controlling PORT65 as IO PORT or a comparator input. 0 IO PORT65 1 comparator input Bit 7 (CMPREF) : Switch for comparator reference voltage type 0 internal reference voltage 1 external reference voltage
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 39
8/23/04 (V1.5)
EM78871 8-bit Micro-controller PAGE2
7 6 VRSEL Bit 0: unused Bit 1 : unused Bit 2 : unused 5 4 3 CW_SMB 2 1 0
Bit 3(CW_SMB) : Call Waiting / short message receiver switch 0 Short message mode select. 5.5% CAS tone accepted frequency range deviation.(Protocol : 5%) 1 Call Waiting mode select. CAS tone accepted frequency range deviation is decided on CODE Option Register bit 5 ( 0:for Europe and USA / 1:for China ) Bit 4 : unused Bit 5 : unused Bit 6 : unused Bit 7 (VRSEL) : Reference voltage VR selection bit for Comparator 0/1 VR = VDD/VR = 2.0V, When this bit is set to "0", V2_0 ref. circuit will be powered off. 2.0V ref. circuit is only powered on when this bit and RD page0 bit 7(CMPEN) are all set to "1".
IOCF (Interrupt Mask Register)
7 6 5 4 RBF/STD FSK/CW INT2 INT1 Bit 0 ~ Bit 7 : Interrupt enable bits. 0/1 disable interrupt/enable interrupt 3 INT0 2 CNT2 1 CNT1 0 TCIF
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 40
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
VII.3 I/O Port
PCRD
Q
P R C L
D CLK PCWR
Q
PORT
Q
P R C L
D CLK PDWR
IOD
Q
PDRD 0 1 M U X
Fig.25 The circuit of I/O port and I/O control register The I/O registers are bi-directional tri-state I/O ports. The I/O ports can be defined as "input" or "output" pins by the I/O control registers under program control. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig.25
VII.4 RESET
The RESET can be caused by (1) Power on voltage detector reset (POVD) and power on reset (2) WDT timeout. (if enabled and in GREEN or NORMAL mode) (3) /RESET pin pull low At case (1), POVD is controlled by CODE OPTION. If you enable POVD, CPU will reset at 2V under. And CPU will consume more current about 3uA . And the power on reset is a circuit always enable. It will reset CPU at about 1.4V and consume about 0.5uA. Once the RESET occurs, the following functions are performed. * The oscillator is running, or will be started. * The Program Counter (R2) is set to all "0". * When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared. * The Watchdog timer and prescaler counter are cleared. * The Watchdog timer is disabled. * The CONT register is set to all "1" * The other register (bit7..bit0)
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 41
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
address R register page0 00xxxxxx xxx00000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000xx0 xxxxxxxx xxxxxxxx 00000000 00000000 00000000 R register page1 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00xxxxxx IOC register page0 IOC register page1 IOC register page2 xxxxxxxx 00000000 00000000 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00000000
4 5 6 7 8 9 A B C D E F
11100000 11111111 11111111 11111111 11111111 00000000 11111111 11111111 00000000 00000000 00000000
00000000 00000000 11111111 11111111 00000000 00000000 00000000 00000000 00000000 00000000 -
VII.5 wake-up
The controller has two types of sleep mode for power saving. (1) SLEEP mode , RA(7)=0 + "SLEP" instruction . The controller will turn off all the CPU and crystal. Other circuit with power control like key tone control or PLL control (which has enable register), user has to turn it off by software.
Wake-up from SLEEP mode (1) DT time out (2) external interrupt (3) /RESET pull low All these cases will reset controller , and run the program at address zero. The status just like the power on reset. Be sure to enable circuit at case (1) or (2).
VII.6 Interrupt
RF is the interrupt status register which records the interrupt request in flag bits. IOCF is the interrupt mask register. TCC timer, Counter1 and Counter2 are internal interrupt source. P70 ~ P77(INT0 ~ INT1) are external interrupt input which interrupt sources are come from the external. If the interrupts are happened by these interrupt sources, then RF register will generate '1' flag to corresponding register if you enable IOCF register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the RF register. The interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts.
VII.7 Instruction Set
Instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register. The symbol "R" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value. INSTRUCTION BINARY HEX MNEMONIC OPERATION STATUS Instruction AFFECTED cycle 0 0000 0000 0000 0000 NOP No Operation None 1
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 42
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
0 0 0 0 0 0 0 0 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0001 0001 0001 0001 0010 0011 0100 rrrr 0000 0001 0010 0011 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 0020 00rr 0080 00rr 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R TBL MOV R,A CLRA CLR R SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b Decimal Adjust A A CONT 0 WDT, Stop oscillator 0 WDT A IOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC Enable Interrupt CONT A IOCR A R2+A R2 bits 9,10 do not clear A R 0A 0R R-A A R-A R R-1 A R-1 R A RA A R R A& RA A&R R ARA ARR A+RA A+RR RA RR /R A /R R R+1 A R+1 R R-1 A, skip if zero R-1 R, skip if zero R(n) A(n-1) R(0) C, C A(7) R(n) R(n-1) R(0) C, C R(7) R(n) A(n+1) R(7) C, C A(0) R(n) R(n+1) R(7) C, C R(0) R(0-3) A(4-7) R(4-7) A(0-3) R(0-3) R(4-7) R+1 A, skip if zero R+1 R, skip if zero 0 R(b) 1 R(b) C None T,P T,P None None None None None None None Z,C,DC None Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z None None C C C C None None None None None None 1 1 1 1 1 1 1 2 2 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 if skip 2 if skip 1 1 1 1 1 1 2 if skip 2 if skip 1 1
0 0000 0001 0100 0 0000 0001 rrrr 0 0000 0010 0000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000 0000 0000 0001 0001 0001 0001 0010 0010 0010 0010 0011 0011 0011 0011 0100 0100 0100 0100 0101 0101 0101 0101 0110 01rr rrrr 1000 0000 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr 00rr rrrr 01rr rrrr 10rr rrrr 11rr rrrr 00rr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr rrrr
0 0110 01rr 0 0110 10rr 0 0110 11rr 0 0111 00rr 0 0 0 0 0 0111 0111 0111 100b 101b 01rr 10rr 11rr bbrr bbrr
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 43
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
0 110b bbrr 0 111b bbrr 1 00kk kkkk 1 1 1 1 1 1 01kk 1000 1001 1010 1011 1100 kkkk kkkk kkkk kkkk kkkk kkkk rrrr rrrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 0001 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1E8k 1Fkk JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT PAGE k ADD A,k if R(b)=0, skip if R(b)=1, skip PC+1 [SP] (Page, k) PC (Page, k) PC kA AkA A& k A AkA k A, [Top of Stack] PC k-A A PC+1 [SP] 001H PC K->R5(4:0) k+A A None None None None None Z Z Z None Z,C,DC None None Z,C,DC 2 if skip 2 if skip 2 2 1 1 1 1 2 1 1 1 1
1 1101 kkkk 1 1110 0000
1 1110 100k kkkk 1 1111 kkkk kkkk
VII.8 CODE Option Register
The controller has one CODE option register which is not part of the normal program memory. The option bits cannot be accessed during normal program execution.
CODE Option Register1 ( Program ROM)
7 6 5 4 3 2 1 /POVD CWMODE PACKSEL1 PACKSEL0 Bit 1~2(PACKSEL0~PACKSEL1) : package select. PACKSEL1 X 1 PACKSEL0 1 0 PACKAGE 132 pin die 128 pin QFPA PS PC0~PC3 floating 0
Bit 3(CWMODE) : CAS tone (2130 Hz plus 2750 Hz ) accepted frequency range select. 0 2% Call waiting accepted frequency range deviation.(Application for China protocol : 1.5% ) 1.2% Call waiting accepted frequency range deviation.(Application for Europe and USA protocol : 0.5% ) 1 Bit 4 (/POVD) : Power on voltage detector, 0/1 enable/disable /POVD 1 0 2.2V /POVD reset voltage No Yes (2.2V) 2.2V Power on reset voltage Yes (2.2V) No Sleep mode current (VDD=5V) 1uA 15uA
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 44
8/23/04 (V1.5)
VII.9 CALL WAITING Function Description
TIP RING
DATA
FSK demodulator
/CD
GAIN CWTIP +
Filter Voltage reference
Detection block
CAS
Vdd/2
Fig.26 Call Waiting Block Diagram Call Waiting service works by alerting a customer engaged in a telephone call to a new incoming call. This way the customer can still receive important calls while engaged in a current call. The CALL WAITING DECODER can detect CAS(Call-Waiting Alerting Signal 2130Hz plus 2750Hz) and generate a valid signal on the data pins. The call waiting decoder is designed to support the Caller Number Deliver feature, which is offered by regional Bell Operating Companies. In a typical application, after enabling CW circuit (by IOC5 page0 bit4 CWPWR) this IC receives Tip and Ring signals from twisted pairs. The signals as inputs of pre-amplifier, and the amplifier sends input signal to a band pass filter. Once the signal is filtered, the Detection block decodes the information and sends it to R3 register bit7 . The output data made available at R3 CAS bit. The data is CAS signals. The CAS is normal high. When this IC detects 2130Hz and 2750Hz frequency, then CAS pin goes to low.
VIII. Absolute Operation Maximum Ratings
RATING DC SUPPLY VOLTAGE INPUT VOLTAGE OPERATING TEMPERATURE RANGE SYMBOL VDD Vin Ta VALUE -0.3 To 6 -0.5 to VDD +0.5 0 to 70 UNIT V V J
EM78871 8-bit Micro-controller
IX. DC Electrical Characteristic
(Operation current consumption for Analog circuit) Parameter Symbol Condition Min Operation current for FSK I_FSK VDD=5V, CID power on VDD=3V, CID power on Operation current for CW I_CW VDD=5V, CID power on VDD=5V, CID power on Operation current for DTMF I_DR VDD=3V, DTMFr power on receiver VDD=3V, DTMFr power on Operation current for TONE I_DTMF VDD=5V, DTMF power on generator VDD=3V, DTMF power on Operation current for Current I_DA VDD=5V, CDA power on DA VDD=3V, CDA power on Operation current for OP I_OP VDD=5V, PT power on VDD=3V, PT power on Operation current for I_CMP VDD=5V, PT power on Comparator VDD=3V, PT power on (Current DA output current) Parameter Current DA output current Typ 2.0 1.8 1.8 1.5 1.8 1.5 0.35 0.15 Max Unit mA mA mA mA mA 0.17 0.1 0.17 0.1 mA mA
Symbol I_DAO
Condition VDD=5V, CDA power on VDD=3V, CDA power on
Min
Typ
Max
Unit mA
(Ta=0C ~ 70C, VDD=5V5%, VSS=0V) Parameter Symbol Condition Input Leakage Current for IIL1 VIN = VDD, VSS input pins Input Leakage Current for IIL2 VIN = VDD, VSS bi-directional pins Input High Voltage VIH Input Low Voltage VIL Input High Threshold VIHT /RESET, TCC, RDET1 Voltage Input Low Threshold Voltage VILT /RESET, TCC,RDET1 Clock Input High Voltage VIHX OSCI Clock Input Low Voltage VILX OSCI Output High Voltage VOH1 IOH = -5mA (port5,8,9,B,C) (port6,7) IOH = -8mA Output Low Voltage VOL1 IOL = 5mA (port5,8,9,B,C) (port6,7) IOL = 8mA Pull-high current IPH Pull-high active input pin at VSS Power down current ISB1 All input and I/O pin at (SLEEP mode) VDD, output pin floating, WDT disabled Low clock current ISB2 CLK=32.768KHz, All analog (GREEN mode) circuit disable , All input and I/O pin at VDD, output pin floating, WDT disabled, LCD * This specification is subject to be changed without notice. 46
Min
Typ
Max Unit 1 A 1 A V V V V V V V V V V A A A
2.0 0.8 2.0 0.8 1.8 1.2 2.0 2.0 0.4 0.4 -15 4
-10 1
50
80
__________________________________________________________________________________________________________________________________________________________________
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
Operating supply current (NORMAL mode) ICC enable /RESET=High, PLL enable CLK=3.579MHz, output pin floating and LCD enable, all analog circuit disable 0.5 1.0 1.3 mA
Tone generator voltage
reference Vref2
0.7
VDD
X. AC Electrical Characteristic
CPU instruction timing (Ta=0C ~ 70C, VDD=5V, VSS=0V) Parameter Symbol Condition Min Input CLK duty cycle Dclk 45 Instruction cycle time Tins 32.768kHz 3.579MHz Device delay hold time Tdrh TCC input period Ttcc Note 1 (Tins+20)/N Watchdog timer period Twdt Ta = 25C Note 1: N= selected prescaler ratio. FSK AC Characteristic (Vdd=5V,Ta=+25C) CHARACTERISTIC FSK sensitivity Low Level Sensitivity Tip & Ring @SNR 20dB High Level Sensitivity Tip & Ring @SNR 20dB Signal Reject FSK twist Positive Twist (High Level) Positive Twist (Low Level) Negative Twist (High Level) Negative Twist (Low Level) CW AC Characteristic (Vdd=5V,Ta=+25C) CHARACTERISTIC CW sensitivity Sensitivity @SNR 20dB Low Tone Frequency 2130Hz High Tone Frequency 2750Hz CW twist Twist Typ 50 60 550 16 16 Max 55 Unit % us ns ms ns ms
Min -40
Typ -48 0 -51
Max Unit dBm dBm dBm dB dB dB dB
+10 +10 -6 -6
Min
Typ -38 1.2 1.2
Max Unit dBm % % dB
7
DTMFr (DTMF receiver) AC Characteristic (Vdd=5V,Ta=+25C) CHARACTERISTIC Min Typ Max DTMFr Low Level Signal Sensitivity -36 High Level Signal Sensitivity 0 Low Tone Frequency 2 High Tone Frequency 2 DTMFr noise endurance Signal to noise ratio 15
Unit dBm dBm % % dB
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 47
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
TONE generators for AC Characteristic (Vdd=5V,Ta=+25C) CHARACTERISTIC Min Typ Max Unit Tone1/Tone2 signal strength (root mean square voltage) Tone1 signal strength V1rms (ps1) 130 155 180 o V o V Tone2 signal strength V2rms (ps1) 1.259V1rms Tone twist (Tone1 - Tone2) twist -2 dB Tone frequency deviation Frequency deviation 1 % (ps1) : V1rms and V2rms has 2 dB difference. It means 20log(V2rms/V1rms) = 20log1.259 = 2 (dB) Timing characteristic (Vdd=5V,Ta=+25C) Description Symbol Min Typ Oscillator timing characteristic OSC start up 32.768kHz Tosc 3.579MHz PLL FSK timing characteristic Carrier detect low Tcdl -10 Data out to Carrier det low Tdoc -10 Power up to FSK(setup time) Tsup -15 End of FSK to Carrier Detect high Tcdh -CW timing characteristic CAS input signal length Tcasi 80 (2130 ,2750 Hz @ -20dBm ) Call waiting data detect delay time Tcwd 42 Call waiting data release time Tcwr 26 DTMF receiver timing characteristic Tone Present Detection Time Tdp (ps1) the guard-times for tone-present Tgtp 30 (C=0.1uF, R=300K) the guard-times for tone-absent Tgta 30 (C=0.1uF, R=300K) Propagation Delay (St to Q) Tpq 8 Tone Absent Detection Time Tda (ps2) SPI timing characteristic (CPU clock 3.58MHz and Fsco = 3.58Mhz /2) /SS set-up time Tcss 560 /SS hold time Tcsh 250 SCLK high time Thi 250 SCLK low time Tlo 250 SCLK rising time Tr 15 SCLK falling time Tf 15 SDI set-up time to the reading edge of SCLK Tisu 25 SDI hold time to the reading edge of SCLK Tihd 25 SDO disable time Tdis (ps1) : Controlled by software (ps2) : Controlled by RC circuit.
Max 400 10 14 20 20 4
Unit ms
ms ns ms ms ms ms ms
ms mS us ms ns ns ns ns ns ns ns ns
30 30
560
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 48
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
XI. Timing Diagrams
ins
Fig.28 AC timing
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 49
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
FIRST RING 2 SECONDS TIP/RING
0.5 SEC
0.5 SEC
SECOND RING 2SECONDS
/ TRIG Tcdl /CD Tdoc DATA (internal clock) Tsup /358E DATA Tcdh
3.579 M Hz
Fig.29 FSK timing diagram
p lu g on
in hook
C AS Tc a s i
events
normal
in use
Tc w d
CAS
Tc w r
CW PW R
power off
power on
Fig.30 Call waiting timing diagram
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 50
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
TONE Tdp 5~20mS by S/W Tgtp 30mS Typ. ST/GT
TONE Tgta 30mS Typ.
EST
Vtst 1/2 VDD Tpq 8 uS Typ.
Q4..Q1
STD
LINE_ENG
Fig.31 DTMF receiver timing diagram
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 51
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
XII. Application Circuit
(Using 871 built-in LCD driver)
LCD pannel
COMMON
VC1 11 0.1u 0.1u 0.1u 0.1u 0.1u VDD 27p 27p 0.1u VC2 12
SEGMENT
Key matrix VC3 13 VC4 14 VC5 15 VDD,AVDD 18,19 XIN 16 32.768k XOUT 17 PLLC 20 AVSS,GND 26,27 28 TEST SEG9 SEG23
SEG10
EM78871
SEG8 30~33 P70 P71 P72 P73 VDD
TIP LINE RING 4700p 4700p 47K
TIP 22 RING 23 47K CWGS 24 CWIN 25 47 EST 46 STGT
47p
150K
39K
4700p
Line Interface
Speech Network
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 52
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
LCD pannel
COMMON
SEGMENT
LCD driver EM9L8580 ( support max 65x132 pixels)
D0..D7 CLK A0 /RD /WR /CS1
8
p65
p60 p61 (SCK) (SD0) 38 39
p63
p64
43 P87~P80 57~64
41
42 SEG23
Key matrix
SEG10 VDD 27p 27p 0.1u VDD,AVDD 18,19 XIN 16 32.768k XOUT 17 PLLC 20 AVSS,GND 26,27 28 TIP LINE RING 4700p 4700p 47K RING 23 47K CWGS 23 CWIN 24 47 EST 46 STGT TIP 22 TEST SEG9
EM78871
SEG8 30~33 P70 P71 P72 P73
VDD
47p
150K
39K
4700p
Line Interface
Speech Network
(Using external EMC LCD driver)
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 53
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
y
: EM78R808 SPEC. (SPEC. is only shown the differences with EM78871)
II.Feature
CPU E Operating voltage range : 2.2Va E 32KN 13 Program ROM E 4MN 8 data ROM. E 8KN 8 data RAM 5.5V
IV.Pin Configuration
SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 COM23/SEG7 COM22/SEG6 COM21/SEG5 COM20/SEG4 COM19/SEG3 COM18/SEG2 COM17/SEG1 COM16/SEG0 COM 15 COM 14 COM 13 COM 12 COM 11 COM 10 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 VC5 VC4 VC3 VC2 VC1 XIN XOUT VDD,AVDD PLLC TONE TIP/EGIN1 RING/EGIN2 CWGS CWIN GND,AVSS /RESET P70/INT0 P71/INT0 P72/INT0 P73 /INT0 P74 /INT1 P75 /INT1 P76 /INT1 P77 /INT2 P60/SCK P61/SDO P62/SDI P63/CMP1 P64/CMP2 P65/CMP3 P66/DAOUT P67/KTONE P55/OP-/STGT P56/OP+/EST P57/OPO ERS CA-1 CA0 CA1 CA2 CA3 CA4
CA5 CA6 CA7 CA8 CA9 CA10 CA11 CA12 CA13 CA14 CD0 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 CD11 CD12 IOD0 IOD1 IOD2 IOD3 IOD4 IOD5 IOD6 IOD7 INSEND IRSEL PH1OUT X2OUT /HOLD ROM EN1 ROM EN2 ROM EN3 ROM EN4 ROM WRITE ROMREAD ROMD0 ROMD1 ROMD2 ROMD3 ROMD4 ROMD5 ROMD6 ROMD7 ROMA0 ROMA1
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 ROMA19 ROMA18 ROMA17 ROMA16 ROMA15 ROMA14 ROMA13 ROMA12 ROMA11 ROMA10 ROMA9 ROMA8 ROMA7 ROMA6 ROMA5 ROMA4 ROMA3 ROMA2
Fig .3
2
EM78R808 pin configuration
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 54
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
VI. Pin Descriptions
PIN POWER VDD AVDD GND AVSS CLOCK XIN XOUT PLLC LCD COM0..COM15 SEG0...SEG7 SEG8..SEG47 SEG48..SEG55 SEG56..SEG63 SEG64..SEG71 SEG72..SEG79 VC1..VC5 I/O POWER DESCRIPTION Digital power Analog power They connect together when package as 128 pin QFP. Digital ground Analog ground They connect together when package as 128 pin QFP. Input pin for 32.768 kHz oscillator Output pin for 32.768 kHz oscillator Phase loop lock capacitor, connect a capacitor 0.01u to 0.047u with GND Common driver pins of LCD drivers Segment driver pins of LCD drivers SEG0 to SEG7 are share with COM16 to COM23 SEG8 to SEG79 are shared with IO PORT.
POWER
I O I
O O (COM16..COM23) O (I/O : PORTB) O (I/O : PORTC) O (I/O : PORT8) O (I/O : PORT9) I
Reference voltage input. Each one connect a capacitor (0.1u) with GND.
FSK , TONE , KTONE TIP I RING I TONE O KTONE O (PORT67) CW O CWGS I CWIN DTMF receiver EST O
Should be connected with TIP side of twisted pair lines for FSK. Should be connected with RING side of twisted pair lines for FSK. Dual tone output pin Key tone output. Shared with PORT67. Gain adjustment of single-ended input OP Amp Single-ended input OP Amp for call waiting decoder
STGT
I/O
Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause EST to return to a logic low. This pin shared with PORT56. Steering input/guard time output (bi-directional). A voltage greater than Vtst detected at ST causes the device to register the detected tone-pair and update the output latch. A voltage less than Vtst frees the device to accept a new tone-pair. The GT output acts to reset the external steering time-constant; its state is a function of EST and the voltage on ST . This pin shared with PORT55. The negative Vin input pin of the OP. This pin shared with PORT55. The positive Vin input pin of the OP. This pin shared with PORT56. The output of OP. This pin shared with PORT57. Master: output pin, Slave: input pin. This pin shared with PORT60. Output pin for serial data transferring. This pin shared with PORT61.
OP OPOP+ OPO SERIAL IO SCK SDO
I (PORT55) I (PORT56) O (PORT57) IO (PORT60) O (PORT61)
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 55
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
SDI Comparator CMP1 CMP2 CMP3 CURRENT DA DAOUT I I I I (PORT62) (PORT63) (PORT64) (PORT65) Input pin for receiving data. This pin shared with PORT62. Comparator input pins. Shared with PORT63, PORT64 and PORT65.
O (PORT66)
Current DA output pin. It can be a control signal for sound generating. Shared with PORT66. PORT 5 can be INPUT or OUTPUT port each bit. PORT 6 can be INPUT or OUTPUT port each bit. Internal pull high. PORT 7 can be INPUT or OUTPUT port each bit. Internal Pull high function. Auto key scan function. Interrupt function. PORT 8 can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. PORT 9 can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. PORT B can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. PORT C can be INPUT or OUTPUT port each bit. Shared with LCD Segment signal. Interrupt sources which has the same interrupt flag. Any pin from PORT70 to PORT73 has a falling edge signal, it will generate a interruption. Interrupt sources which has the same interrupt flag. Any pin from PORT74 to PORT76 has a falling edge signal, it will generate a interruption. Interrupt source. Once PORT77 has a falling edge or rising edge signal (controlled by CONT register), it will generate a interruption. Low reset System clock output. CA-1 is used as address line to select low-order data (8 bits, through CD0~CD7) or high-order data (5 bits, through CD0~CD4) ERS=1 => CA-1 NO USE ERS=0 => CA-1=0 HIGH ORDER DATA CA-1=1 LOW ORDER DATA Input pin used to select the external ROM data bus through bus CD0~D12 or CD0~CD7 only. HIGH/LOW = CD0~CD12 / CD0~CD7. Program code address bus. CA0~CA14 are address output pins for external programming ROM access. Data access in terms of CA0 ~ CA12 addressing. IRSEL is an output pin used to select an external EVEN/ODD ROM. Used to indicate the instruction completion and ready for next instruction. Microcontroller hold request. I/O data bus.
IO P55 ~P57 P60 ~P67 P70 ~ P77
I/O I/O I/O
P80 ~ P87 P90 ~ P97 PB0 ~ PB7 PC0 ~ PC7 INT0
I/O I/O I/O I/O PORT70..73
INT1
PORT74..76
INT2 /RESET X2OUT CA-1
PORT77 I O O
ERS
I
CA0~CA14 CD0~CD12 IRSEL INSEND /HOLD IOD0~IOD7
O I O O I O
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 56
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
PH1OUT O Phase 1 output
ROMA0..RO MA19 ROMD0..RO MD7 ROMEN1..R OMEN4
O IO O
External data ROM address External data ROM data bus Data ROM enable pin. User can select one of four external DATA ROM by these enable signal. Please refer to RB address of data ROM. ROMA21,ROMA20 00 01 10 11 ROMEN4, ROMEN3, ROMEN2, ROMEN1 1,1,1,0 1,1,0,1 1,0,1,1 0,1,1,1
ROMREAD ROMWRITE
O O
External data ROM reading signal. Normal high . When you read data ROM, it will generate a low pulse a instruction long. External data ROM writing signal. Normal high . When you write data ROM, it will generate a low pulse a instruction long.
VII Operational Registers
R9 PAGE1 (LCD address MSB bit, Data ROM address bits)
7 6 5 4 3 2 1 0 LCDA8 DROM_A21 DROM_A20 DROM_A19 DROM_A18 DROM_A17 DROM_A16 Bit 0~Bit 5(DROM_A16~DROM_A21) : Data ROM address(16~21) for ROM reading. Bit 6 : unused Bit 7(LCDA8) : MSB of LCD address for LCD RAM reading or writing Other LCD address bits LCDA7 ~ LCDA0 are set from RA PAGE1 Bit 7 ~ Bit 0. For LCD address access over 0xFFH, set this bit to "1"; otherwise set this bit to "0".
IOC5 PAGE2 ( Stack Pointer )
7 6 5 4 3 2 1 0 STKF STKM STKP5 STKP4 STKP3 STKP2 STKP1 STKP0 Bit 0~Bt 5(STKP0~STKP5) : Stack Point selection bits( User must enable CODE Option Register bit 2 before using Stack pointer function ) Stack5 0 0 0 0 0 0 0 0 1 : Stack4 0 0 0 0 : : 1 1 0 : STKP3 0 0 0 0 : : 1 1 0 : STKP2 0 0 0 0 : : 1 1 0 : STKP1 0 0 1 1 : : 1 1 0 : STKP0 0 1 0 1 : : 0 1 0 : Stack Point Stack 0 Stack 1 Stack 2 Stack 3 : : Stack 30 Stack 31 Stack 32 :
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 57
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
User can read bit 5 .. bit 0 to understand how many stack layer that program used . Bit 5 .. bit 0 is a six bit counter. The counter will incrementally after user use internal , external interrupt or "CALL" instruction and it will decrement when user use "RET" or "RETI" instruction. When Bit6(STKM) is set to 1 and bit 5 .. bit 0 are 0b011110 0b011111 , interrupt will occur. Bit 6(STKM) : Stack overflow mask bit. 0 STK interrupt disable. 1 STK interrupt enable. Bit 7(STKF) : Stack Point overflow interrupt flag bit. STKF will set to 1 when bit 5 .. bit 0 are 0b011110
0b011111
IX
AC Electrical Characteristic
Tdiea 30 30 30 30 100 20 20 30 ns ns ns ns ns ns ns ns
Delay from Phase 3 end to Cl=100pF INSEND active Tdiei Delay from Phase 4 end to Cl=100pF INSEND inactive Tiew INSEND pulse width Tdca Delay from Phase 4 end to CA C1=100pF Bus valid Tacc ROM data access time Tcds ROM data setup time Tcdh ROM data hold time Tdca-1 Delay time of CA-1 C1=10 0pF Note 1: N= selected prescaler ratio.
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 58
8/23/04 (V1.5)
EM78871 8-bit Micro-controller
E R S =1 , CA-1 =D IS AB LE
3 4 1 2 3 4 1 2 3
CLK
Td ie i Td ie a
/INSEND
Tie w Td c a
CA 14 : 0
Ta c c Tc d s Tc d h
CD 12 : 0
E R S =0 , CA-1 =0 H IGH OR D E R D AT A CA-1 =1 LO W OR D E R D AT A
3 4 1 2 3 4 1 2 3
CLK
Td ie a Td ie i
/INSEND
Td c a 1 Tie w
CA-1
Td c a
CA 14 : 0
CD 7 : 0
Ta c c Tc d s
High order DATA
Tc d h
Low order DATA
Fig.33 Program ROM access timing
__________________________________________________________________________________________________________________________________________________________________
* This specification is subject to be changed without notice. 59
8/23/04 (V1.5)

▲Up To Search▲

Price & Availability of EM78871H

	To Download EM78871H Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .